1. Field of the Invention
The present invention relates to a stacked semiconductor device, and more particularly to a stacked semiconductor device having a defective contact recovery means for recovering a defective contact between stacked semiconductor chips.
2. Description of the Related Art
Recently, semiconductor memory devices including a dynamic random access memory (DRAM) have increasingly been required to have a larger memory capacity and to operate at a higher speed. An increase of a memory capacity of semiconductor memory devices has been achieved mainly by reduction of a memory cell size and enlargement of a chip size. However, the reduction of a memory cell size has a physical limitation. Further, the enlargement of a chip size causes a lowered yield and prevents a speed-up of a semiconductor memory device. Thus, a stacked semiconductor device having a plurality of stacked semiconductor chips has been proposed to fundamentally resolve the above problems. Such a stacked semiconductor device has semiconductor substrates and through electrodes extending through the semiconductor substrates for electrically connecting semiconductor chips to each other. With a plurality of stacked semiconductor chips, it is possible to achieve an increase of a memory capacity and a compactness of a semiconductor device.
There has been proposed a method of stacking core chips with a memory cell and an interface chip with a peripheral circuit for the memory cell, and transmitting and receiving signals via through electrodes extending through the chips (see Patent Document 1: Japanese laid-open patent publication No. 2004-327474). With this method, a semiconductor memory device, which has heretofore had one chip, is divided into a plurality of chips. Accordingly, it is possible to remarkably reduce a size of each chip. Thus, this method is expected to achieve a higher yield and a larger memory capacity of a semiconductor memory device. Further, an interface portion can be manufactured by a logic process. Generally, a transistor manufactured by a logic process can operate at a speed higher than a transistor manufactured by a memory process. Therefore, circuits in the interface portion can operate at a high speed. As a result, it is possible to achieve a speed-up of a semiconductor memory device.
FIG. 1 shows such a stacked semiconductor device. The stacked semiconductor device shown in FIG. 1 comprises an interface chip 102, a plurality of core chips 101a to 101c, and an interposer 100. Each of the core chips 101a, 101b, and 101c has a large number of memory cells such as DRAMs, a circuit for storing data in the memory cells, and a control circuit for the memory cells and the aforementioned circuit. Specifically, each of the core chips 101a, 101b, and 101c includes circuits such as a sense amplifier and an address decoder as peripheral circuits of the memory cells, a control circuit for adjusting operation timing of those circuits, an input/output circuit for the interface chip 102, a circuit required for determination of non-defective products in a wafer test for core chips, and the like. Further, each of the core chips 101a, 101b, and 101c has through electrodes 12 extending through the chip.
The interface chip 102 includes an external input/output circuit 16 and an internal signal input/output circuit 15 formed thereon. The external input/output circuit 16 is operable to perform a data transfer with an external terminal 103. The internal signal input/output circuit 15 includes an address buffer, a refresh counter, and the like and is operable to perform a data transfer with the core chips 101a to 101c. Thus, the interface chip 102 serves to relay an external signal to the core chips 101a, 101b, and 101c and relay a signal from the core chips 101a, 101b, and 101c to an exterior of the semiconductor device. The interposer 100 has an external terminal 103 formed on a rear face of the interposer 100, a metal interconnection 30 formed on a substrate, and a means for connecting a contact portion of the core chip 101c to the external terminal 103 via the metal interconnection 30 on the substrate.
In FIG. 1, the core chips 101a, 101b, and 101c are stacked on the interposer 100. The interface chip 102 is stacked on the uppermost core chip 101a. The respective layers (chips) are connected to each other by contact portions 11 between the chips and the through electrodes 12. External signals are transmitted and received through a signal path 1 connected to the external terminal 103 formed on the interposer 100. Internal signals are transmitted and received through a signal path 2 connected to the interface chip 102 and interiors of the core chips 101a to 101c. In the stacked core chips 101a to 101c, the through electrodes 12 of the chips are connected to each other by the contact portions 11 between the chips. Accordingly, the through electrodes 12 and the contact portions 11 between the chips, which form each signal path, are collectively referred to as a contact group. The contact portions 11 between the chips may employ solder balls or the like.
In a stacked semiconductor device, when a plurality of semiconductor chips are stacked, a defective contact may be produced by faults of through electrodes extending through the chips or faults of contact portions connecting the chips to each other. Even though each of the semiconductor chips is a non-defective product, a stacked semiconductor device becomes a defective product if one defective contact is produced in the stacked semiconductor device. This problem is caused by the fact that a defective contact cannot be repaired so as to revive a stacked semiconductor device.
A plurality of chips are bonded to each other by a solder ball or the like to produce a stacked semiconductor device. If the bonded chips are separated from each other, the fused solder ball is attached to the through electrodes of the chips. Technology of completely removing the attached solder ball or technology of re-stacking the chips to which the solder ball is attached has not been established yet. Accordingly, in a stacked semiconductor device having a plurality of stacked chips, the stacked semiconductor device may be determined to be defective because of one defective contact. In other words, all of the stacked chips are determined to be defective. Thus, a yield of stacked semiconductor devices is problematically decreased.
Further, Japanese laid-open patent publication No. 2004-152811 (Patent Document 2), Japanese laid-open patent publication No. 2004-152812 (Patent Document 3), International publication No. WO97/11492 (Patent Document 4), Japanese laid-open patent publication No. 2004-095799 (Patent Document 5), and Japanese laid-open patent publication No. 2004-152810 (Patent Document 6) refer to a stacked semiconductor device. Patent Document 2 discloses through electrodes connecting between only a portion of semiconductor chips when locations of the through electrodes are different in stacked semiconductor chips. Patent Document 3 discloses a plurality of through electrodes having different permissible current capacities for one signal. Patent Document 4 discloses removing a defective macro portion in a semiconductor chip and bonding a recovery macro at the removed portion by a metal thin film. Patent Document 5 discloses inserting a wiring base material between stacked semiconductor chips and supplying a signal from an interlayer wiring line via the wiring base material to the semiconductor chips. Patent Document 6 discloses through electrodes having varied cross-sectional areas for a power source, for a ground, and for a signal.
Thus, the above-mentioned references disclose a variety of technologies for a stacked semiconductor device. However, these references fail to disclose the problem that a yield of a stacked semiconductor device having a plurality of stacked chips is lowered by only one defective contact. The above-mentioned references do not consider such a problem and do not provide any technical suggestion to solve the problem.